First, I noticed that some signals has prefix like MUX, IF, but some other signals does not, so when will the bsc generate some signals with prefix? Second, a lot of signals is named by an index number, like `hxxxxxx`, how can I figure out what the coresponding signal in the original BSV files? Third, can I forec bsc to keep a BSV variable's name not changed in the output verilog file? this sometimes can help fix timing a lot. Thanks.

Hello, I'm having an issue trying to get Bluespec Verilog to insert registers that are clocked on the negative edge of a the domain clock. I've used the mkClockInverter module, synchronizers and other sort of tricks to try and get the desired result I'd like. Most of my first attempts resulted in errors out of the compiler talking about clock ancestry (I don't expect this since they should have the same ancestor), reset synchronizers (which I did try to fix), or just simple type errors looking to get around this. I finally settled on using the mkSyncBit05 module with both clocks being the same domain SyncBitIfc #(Bit #(1)) rg_din <- mkSyncBit05(sclk, srst_b, sclk); . This kind of makes these a bit wonky, but it seems to work for my purpose. My question to you all is: what is the Bluespec recommended way to properly implement registers that utilize the falling edge of a clock? Thanks!

When I use BVI to import a Verilog module, I found that it can only be used in verilog backend, and not in bluesim backend. After doing some searching, I found that in the bsc's user guide section Imported Verilog modules in Bluesim, it said that there are two environment variables called `genC` and `genVerilog`, which can be used to write a wrapper to decide whether to create a BVI instance or a bluesim instance. But I also read the source code of BRAM module in the standard library, it also uses BVI to import verilog files, but doesn't use the two environment variables. But we can still use BRAM module in both bluesim and verilog backend. So, why my own code that import BVI need a wrapper, but BRAM module need not? It there some logic that I ignored? Thanks.

I have compared the generated verilog file with interface with and without `("reg")` attribute, but the generated verilog file is the same. So, why need to label that a port is a reg I/O? Thanks.

There seems no documents about how to select different verilog primitive for differnet backend tools(like Vivado), so I have to ask some questions and hope these will somehow included in the document. First question: I have noticed that BSV has support for Vivado and Quartus(there are Verilog.Quartus and Verilog.Vivado directory), but how to select which to use? In the release note of 2021.07 release, I found it said that I can define a macro called VIVADO to select target tool, but I can't figure out how it works. Does this macro only affect bluesim backend, but not verilog backend? Second question: In the doc of SpecialFIFOs, it says that 'The SpecialFIFOs package contains various FIFOs provided as BSV source code, allowing users to easily modify them to their own specifications'. So, how to do the "easily modify"? Does that means I have to modify the verilog source code provided in BSV's install dir? Third Questin: Maybe this one is the root cause of the pervious two. I am using 'listVlogFiles.tcl' to collect all necessary verilog files for the backend tool to use, so, how to make 'listVlogFiles.tcl' know that a BRAM2.v has to come from `Verilog.Vivado` directory instead of the default `Verilog` directory? Fourth Question: I am using Achronix's FPGA now and found that it has many differnces like it's BRAM is a `Simple Dula Port BRAM` which means it has one read-only port and one write-only port, so it doesn't fit the BRAM library's interface. If I want to contribute some code for Achronix's FPGA, how and where can I start? Thnaks!

Since this is a different issue, I will start a new thread. However, it is a simple problem and I know the solution. After updating from Fedora 39 to 40, I get the following error. /usr/local/lib/Bluesim/bs_prim_mod_reg.h:22:14: 警告: template-id not allowed for constructor in C++20 [-Wtemplate-id-cdtor] 22 | MOD_Reg<T>(tSimStateHdl simHdl, const char* name, Module* parent, | ^~~~~~~~~~~~ /usr/local/lib/Bluesim/bs_prim_mod_reg.h:22:14: 備考: remove the ‘< >’ ChatGPT's response is shown. The warning you're seeing is due to the fact that in C++20, a template-id is not allowed for a constructor. You need to remove the template parameters from the constructor declaration. Here's how you can modify your code to resolve this issue: Original code: template <typename T> class MOD_Reg { public: MOD_Reg<T>(tSimStateHdl simHdl, const char* name, Module* parent, T initVal); // Other member functions and variables }; Modified code: template <typename T> class MOD_Reg { public: MOD_Reg(tSimStateHdl simHdl, const char* name, Module* parent, T initVal); // Other member functions and variables }; In the modified code, the `<T>` template-id has been removed from the constructor declaration. This change makes the code compliant with C++20 and resolves the warnings. If you have similar issues in other parts of your code, you should apply the same change by removing the template-id from constructor declarations. After modifying the header file as suggested here, the error is gone and it works fine. Please confirm. -- SAKURAI, Atsushi <sakurai@...>

When using `mkFIFO` to build pipelines and when the pipeline is very deep and complex, it's hard to make it fully-pipelined. And to make it fully pipelined, a lot of fine tuning of fifo deepth is required. Is there any similar tools that can achieve the same function like SpinalHDL's Automated Operand Latency Matching which is described at https://tomverbeure.github.io/rtl/2018/12/01/SpinalHDL-Automated-Operand-Latency-Matching.html

The polynomial for mkLFSR in the document do not match the ones listed at https://en.wikipedia.org/wiki/Linear-feedback_shift_register#Example_polynomials_for_maximal_LFSRs Will the ones listed in the above link work as the primitive polynomials for mkFeedLFSR? or does mkLFSR use a different architecture? If it uses a different arch where can I find the details of the polynomials required by it?

In my design the Bluespec code is embedded inside the parent verilog code. I am getting configuration data via a method. since this data is written to the registers via software, other than the start signal all other signal are assumed synchronized. I am trying to define this via ``` SyncPulseIfc sync_start <- mkSyncPulseFromCC(dst_clk); Wire#(CFG_Reg_Read_st) csr_rd <- mkDWire(unpack(0)); ReadOnly#(CFG_Reg_Read_st) cfg_dst <-mkNullCrossingWire(dst_clk,csr_rd); rule syncStart(csr_rd.ctrl.start); sync_start.send(); endrule method Action cfg(CFG_Reg_Read_st x); csr_rd <= x; endmethod ``` This results in the following error message ``` Error: "Clocks.bsv", line 1743, column 9: (G0005) The assertion `can_schedule_first' failed for rule `RL_cfg_dst_clock_domain_crossing' because before it can be executed: cfg must be executed ``` I understand that the compiler is expecting cfg_dst instantiation to be scheduled before the cfg method. But I am at a loss on how to achieve this. Is this possible? or should I write the synchronization logic module in plain verilog?

Somewhere in my code I am doing error = actual != expected; where actual =3'bxxx and expected is 3'b0 This results in error getting a value of x Is there an operator in bluespec equivalent to verilog's === ?

Is there any way to lift Bluespec into a Theorem prover such as Coq or others?

For the interface: interface TwoSorterInterface = unsorted :: Vector.Vector 2 (Bit 32) -> Action {-# prefix="", arg_names = [unsorted] #-} sorted :: Vector.Vector 2 (Bit 32) I get the following Verilog: module mkTwoSorter(CLK, RST_N, unsorted, sorted); input CLK; input RST_N; // action method unsorted input [63 : 0] unsorted; // value method sorted output [63 : 0] sorted; but what I really want are ports like either of these which keep the nested vector structure from the Bluespec: input [31:0][7:0] unsorted output [31:0] sorted[8] Is that possible? Not a big deal if not, I can manually write a SystemVerilog wrapper. Many thanks. Satnam

I tried to build from HEAD this morning, but got this GHC panic. Has someone else encountered this and already reported a GHC bug? Any recommendation for a version of GHC to use? Thank you kindly. Satnam [178 of 224] Compiling GenABin ( GenABin.hs, /net/home/ssingh/bsc/src/comp/../../build/comp/GenABin.o ) ghc: panic! (the 'impossible' happened) (GHC version 9.2.8: heap overflow Please report this as a GHC bug: https://www.haskell.org/ghc/reportabug

I'm trying to use ∘ e.g. riffle :: Vector n a -> Vector n a riffle = unpairs ∘ uncurry zip ∘ halve but I get this error: bsc -sim -g twoTwoSorter -u BitonicSorter.bs checking package dependencies Error: "./Combinators.bs", line 25, column 18: (P0002) Bad character in input: '\136' make: *** [Makefile:11: sorter] Error 1 I see it in the Prelude and the BitonicSorter example.... should this work? Thank you kindly. Satnam Satnam

Still trying to remember everything I have forgotten about BH, I am having problems running a Bluesim simulation when I rename CLK and RSTN. The generated Verilog testbench works just fine (but then I made the appropriate changes to my top-level Verilator driver C++ program). The Bluesim binary just hangs with no output, so I guess I have forgotten to do something? Also, I can't recall how to use a positive reset instead of a negative reset. Thank you kindly. {-# verilog mkWombatTest #-} {-# properties mkWombatTest = { alwaysReady, alwaysEnabled, CLK = clk, RSTN = rstn } #-}

I wanted to write a literal for a `Vector`in Bluespec Classic (BH) (I know this is well supported in BSV) and this is as close as I could get (thank you Greg): ``` vals :: List (Bit 32, Bit 32) vals = Nil <: (12, 5) <: (4, 7) <: (9, 5) <: (75, 14) valsVec :: Vector.Vector 4 (Bit 32, Bit 32) valsVec = Vector.toVector vals ``` Is there a better way? There does not seem to be a `<:` for `Vector`? That's why I made a `List` and then converted it to a `Vector`. Is there a technical reason why `Vector` lacks `<:`. Thank you. Satnam

I want to get the runtime state for some queues to help me debug why some rules run into deadlocks. I want to write a tcl script to automate it by examining all the rule's fire condiditon. With bluetcl, I can use `Bluetcl::rule full` to get the predicate, I found the returned predict mainly has to forms, one is something like `foo.read == xxx`, another is something like `someQueue.notEmpty` For the first form of predict condition, I can use `Bluetcl::sim lookup` and `Bluetcl::sim get` to get its runtime value, but for the second form, I don't known how to get it's value (i.e., the return value of the interface's method). By the way, there is another question with `Bluetcl::sim ls *`, which will give something like `{b__h1062 signal} {b__h11291 signal} {b__h1352 signal}`, where can I find out what does those signal names map to the source code? thanks!